ASIC interview Question & Answer

A blog to collect the interview questions and answer for ASIC related positions

Thursday, November 4, 2010

SystemVerilog Q&A

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1.  What's difference between static and automatic task/program?     If you use static task for multiple places in your testbench,  th...
1 comment:
Sunday, October 31, 2010

Systemverilog Assertion (SVA) 2

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Working Assertion Examples: Normal inline assertion example: assertStateStartShortFalse:   assert property (@(posedge clk) disable iff(...

SVA ( System verilog Assertion)

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1.  What are difference between SVA and other assertions? Answer: Systemverilog Assertions (SVA) are temporal, Declarative and formal frie...
1 comment:
Saturday, June 5, 2010

SystemVerilog Interview Questions

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1.   How many array types in SystemVerilog? How do you use them?       array_name[ ]  dynamic array       e.g .   dyna_arr_1 =   new [ 1...
1 comment:
Wednesday, June 2, 2010

New interview questions

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1) There is a waveform     in _____|====|________     out_____|=|___|=|______     The output is "high" when the input change ...
Sunday, May 30, 2010

C++ basic interview questions

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1) How do you swap two integers? Without another variable? Answer:    example main.cpp    void main()    {       int a=2, b=3;     ...
1 comment:

C++ Interview algorithms questions

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1) Reverse a single linked list Answer code: Node* ReverseList(Node ** List)       // Provide a link list {       // Declare 3 pointer...
4 comments:
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About Me

Roy Chan
Specialties in ASIC Design and Verification from front-end to back-end activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new career.
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