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A blog to collect the interview questions and answer for ASIC related positions
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- ASIC Flow (1)
- ASIC Gate (3)
- ASIC Logic (4)
- ASIC SystemVerilog (10)
- ASIC timing (2)
- ASIC Verification (1)
- C++ (2)
- Design Complier (1)
- Memory Interface (1)
- Networking (2)
- perl (9)
- PLL (1)
- Previous Interview Questions (1)
- PrimeTime (1)
- SVA (2)
- Verilog Interview Questions (6)
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About Me
- Roy Chan
- Specialties in ASIC Design and Verification from front-end to back-end activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new career.