ASIC Logic Interview Questions Part #4

1) Design a Gray counter to count 6.

   The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system where two successive values differ in only one bit.

Dec Gray Binary
0 000 000
1 001 001
2 011 010
3 010 011
4 110 100
5 111 101
6 101 110
7 100 111


module gray_counter (
out , // counter out
enable , // enable for counter
clk , // clock
rst // active hight reset
);

//------------Input Ports--------------
input clk, rst, enable;
//----------Output Ports----------------
output [ 2:0] out;
//------------Internal Variables--------
wire [2:0] out;
reg [2:0] count;
//-------------Code Starts Here---------
always @ (posedge clk)
if (rst)
count <= 0;
else if (enable)
  begin
  if(count < 3'b101)
 count <= count + 1;
else
count <= 0;

end
assign out = { count[2], (count[2] ^
count[1]),(count[1] ^ count[0]) };

endmodule

ASIC Logic Interview Questions Part # 3

1) Create "AND" Gate using a 2:1 multiplexer. ( Create all other gates too)


Answer:



   Z = XS + Y/S


  If  X=0, Y=1,
    Z =  /S    ( Inverter gate)

  If X=1, Y=0,
   Z = XS   ( AND gate )

   With AND gate and inverter, it's a basic building gate NAND.



2) What is the minimum logic gates required to generate any boolean function?

Answer:




NAND and NOR are the universal gates. They can created any gates as following:


Use NAND to create an inverter




Use NAND to create a NOR gate



Use NAND to create a XOR gate



XNOR can be created with additional inverter.

ASIC Logic Interview Questions Part # 2

1) 

Draw the state diagram for a circuit that outputs a "1" if the aggregate serial binary input is divisible by 5. For instance, if the input stream is 1, 0, 1, we output a "1" (since 101 is 5). If we then get a "0", the aggregate total is 10, sowe output another "1" (and so on).

Answer:

    The number is divided by 5 , it doesn't matter if it's 25 or 0.

    We need to keep tracks of "0" to "4"

2) How to design a divided by 2 clock and divided by 3 clock with 50% duty cycles?

 Answer:

  The divided by 2 clock is as following:

The divided by 3 clock with 50% duty cycle is as following:

ASIC Logic Interview Questions Part # 1

1) Draw the gate level diagram of the NAMD and list the table with four different inputs [ 0, 1, z, x]?

 Answer:




The inputs are only  four different types [0, 1, z, x]. Assume inputs are A and B, C as output. The truth table are as following:

Input A	Input B	Output C	Comments
0	0	1
0	1	1
1	0	1
1	1	0
0	Z	1	The p-gate turn on with "0" input, the "z" input has no effect on n-gate.
Z	0	1	The p-gate turn on with "0" input, the "z" input has no effect on n-gate.
1	Z	X	The p-gate is off with "1" input, but the "z" input has no effect on n-gate. The result is unknown.
Z	1	X	The p-gate is off with "1" input, but the "z" input has no effect on n-gate. The result is unknown.
Z	Z	X	The "z" input has no effect on both p-gate and n-gate. The result is unknown.
0	X	X	The p-gate turn on with "0" input, the "X" input has unknown effect on n-gate. The result is unknown.
X	0	X	The p-gate turn on with "0" input, the "X" input has unknown effect on n-gate. The result is unknown.

Can we put Z on the output C?

Answer:

For this circuit, it's impossible. Both inputs A and B are tied with p-gate and n-gate. There's no way to put both "0" and "1" in the same input A or input B.


2) Write the verilog code to create the following patterns:
       000->001->010->100->000->001.......
    
Answer:

   reg [0:2] result;
   reg [0:3] temp;

   always@(posedge clk or reset)
   begin
      if(!reset)
      begin
        temp= 4'b0001;
        result = 3'b000; 
      end
    else
     begin
         result <= temp[2:0];
         temp << 1;  // shift 1 bit to the left
         temp[3] = temp[0];  // make the chain connected
     end 
 end

3) Given the following FIFO and rules, how deep does the FIFO need to be to

   prevent underflowing or overflowing?

c

RULES:
   1) frequency(clk_A) = frequency(clk_B) / 4
   2) period(en_B) = period(clk_A) * 100
   3) duty_cycle(en_B) = 25%

Answer:

Assume clk_B is 100Mhz ( 10ns )

From rule 1, clk_A = clk_B/4 = 25MHz ( 40ns )

From rule 2, period (en_B) = clk_A*100 = 40ns * 100 = 4000ns

From rule 3, duty_cycle(en_B) is 25%, so it's only 1000ns.  3000ns does not output anything.

Therefore, the FIFO size = 3000ns/40ns = 75 entries.


4)  Draw a state diagram to detect the sequence "0110" ( the leading 0s cannot be used in more than one sequence).

 Answer:

State machine

always (@posedge clk or reset_n)
begin
  if(!reset_n)
  begin
      reset statement
  end
  else
  begin
  case(state)
  S0:
  S1:
  default:
  end
end