SystemVerilog Q&A

1.  What's difference between static and automatic task/program?

    If you use static task for multiple places in your testbench,  the local variables will share the common, static storage. In this case, different threads will step on each other's values.
   By using atuotmic storage, it will make a copy of local variables and use them. Not a common static storage any more.

  e.g.  program automatic initialization;
         ......
        endprogram


2. What's the packed array and unpacked array?

    unpacked array is an array with gap between variables.

   e.g.  bit[7:0]  b_unpack[3];   // unpacked
          The system verilog simulators store each element on a 32-bit word boundary. In other words, you are using only lower 8 bits, the other 24 bits per word space is wasted.

    Packed array is an array without gap. Unpacked array is good for local individual variable access.

   e.g. bit[3:0] [7:0] bytes; // 4 bytes packed into 32 bits

    In this case, all 32 bits word are packed with 4 bytes. A packed array is handy if you need to convert to and from scalars.

3.  What's different between logic and wire?

     Logic and wire are almost the same except wire can be driven by multiple sources. Logic can only driven by single source.