Wednesday, April 21, 2010

SystemVerilog Interview Questions 7

1)  Difference between Associative array and Dynamic array ?


    Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically.
    e.g.            int array[];
    When the size of the collection is unknown or the data space is sparse, an associative array is a better option. In associative array, it uses the transaction names as the keys in associative array.
   e.g.            int array[string];

2)  What are the advantages of SystemVerilog DPI?

SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). The DPI provides a very simple, straightforward, and efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI. 

3)  What is bin?

A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions.

program main;
    bit [0:2] y;
    bit [0:2] values[$]= '{3,5,6};
    covergroup cg;
      cover_point_y : coverpoint y
                      { option.auto_bin_max = 4 ; }
    cg cg_inst = new();
         y = values[i];

4) What are void functions ?

The function does not have return value

5)   What is coverage driven verification?

Coverage Driven Verification is a result oriented approach to functional verification. The manager and verification terms define  functional coverage points, and then work on the detail of process.
Used effectively coverage driven verification focuses the Verification team on measurable progress toward an agreed and comprehensive goal.

6)  Explain about pass by ref and pass by value?
Pass by value is the default method through which arguments are passed into functions and tasks. Each subroutine retains a local copy of the argument. If the arguments are changed within the subroutine declaration, the changes do not affect the caller.

In pass by reference functions and tasks directly access the specified variables passed as arguments.Its like passing pointer of the variable.

task pass(int i)    //  task pass(var int i) pass by reference
i = 1;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
i = 2;
printf(" i is changed to %d at %d\n",i,get_time(LO) );

7)  What is the difference between program block and module ?

The module is the basic building block in Verilog which works well for Design. However, for the testbench, a lot of effort is spent getting the environment properly initialized and synchronized, avoiding races between the design and the testbench, automating the generation of input stimuli, and reusing existing models and other infrastructure.

Systemverilog adds a new type of block called program block. Systemverilog adds a new type of block called program block. The program construct serves as a clear separator between design and testbench, and, more importantly, it specifies specialized execution semantics in the Reactive region for all elements declared within the program. Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench, and enables cycle and transaction level abstractions.

8)   Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them.

      Code Coverage indicates the how much of RTL has been exercised. The Functional Coverage indicates which features or functions has been executed. Both of them are very important.  With only Code Coverage, it may not present the real features coverage. On the other hand, the functional coverage may miss some unused RTL coverage.



  1. It was a very helpful material. Excellent answers.

    Gopi Krishna
    Author of

    1. Hi Gopi,

      The website is very helpful, but it looks like it is down for now. Any idea when will it be fixed?

  2. Hi

    I read this post two times.

    I like it so much, please try to keep posting.

    Let me introduce other material that may be good for our community.

    Source: Basic interview questions

    Best regards

  3. Adding more explonation for question 6.
    While using the pass by reference in SV, we need to use the keyword "ref" in declaration part as below.
    task pass(ref int i)


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  6. I really liked your blog. I have found similar blog with more number of interview questions.

  7. 2. Hi There,

    Fully agree on ASIC interview Question & Answer. We’re seeing a lot of projects tackle big complex problems but few seem to have taken into consideration and in particular reasons to adopt.

    Could someone explain how to write a function to access and display head node in a one node linked list only? I am learning linked list of my own and I am stuck there. Can someone explain it urgently?

    I read multiple articles and watched many videos about how to use this tool - and was still confused! Your instructions were easy to understand and made the process simple.



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