SystemVerilog Interview Question 5

1) What is the use of modports ?

Answer:
Modport restrict interface access within a module based on the direction declared. Directions of signals are specified as seen from the module.

e.g.
interface intf (input clk);
        logic read, enable,
        logic [7:0] addr,data;
       
        modport dut (input read,enable,addr,output data);
        modport tb (output read,enable,addr,input data);
    endinterface :intf

2) How parallel case and full cases problems are avoided in SV?

The full_case and parallel_case directives are dangerous because they tell the synthesis tool
something different about the design than what is told to the simulator.

To the Verilog simulator, full_case and parallel_case are buried inside of Verilog
comments and are completely ignored. To the synthesis tool, full_case and parallel_case
are command-directives that instruct the synthesis tools to potentially take certain actions or
perform certain optimizations that are unknown to the simulator.


A full case statement is a case statement in which all possible case-expression binary patterns
can be matched to a case item or to a case default.

e.g. Full case, sel=2'b11 will be covered by default statement.
     The x-assignment will also be treated as a don'tcare for synthesis, which may allow the synthesis tool to further optimize the synthesized design. It's the potentially causing a mismatch to occur between simulation and synthesis. To insure that the pre-synthesis and post-synthesis simulations match, the case default could assign the y-output to either a
predetermined constant value, or to one of the other multiplexer input values

module mux3c
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule


// Use synopsys full_case statement to create the full case , but it treated differently in simulation and synthesis.
module mux3b (y, a, b, c, sel);
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel) // synopsys full_case
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
endcase
endmodule

SystemVerilog use priority modified case statement to solve the full case problem.
The biggest difference between a full_case directive and a priority modified case statement
is that the priority keyword is part of the SystemVerilog syntax that will be interpreted the
same by simulators, synthesis tools and formal verification tools. In essence, the priority case
statement is a "safe" full_case case statement.

e.g.
priority case (...)
...
endcase

A parallel case statement is a case statement in which it is only possible to match any case
expression to one and only one case item.

e.g. A parallel case statement

module intctl1b
(output reg int2, int1, int0,
input [2:0] irq );
always @* begin
{int2, int1, int0} = 3'b0;
casez (irq) // synopsys parallel_case
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule

This is an example that demonstrates that adding the parallel_case directive makes the design
smaller and faster, but in the process it also adversely changes the functionality of the design.

SystemVerilog adds the new case statement modifier called "unique."
The unique keyword shall cause the simulator to report a run-time error if a case expression is
ever found to match more than one of the case items. In essence, the unique
case statement is a "safe" parallel_case case statement.

unique case (...)
...
default: ...
endcase

Guideline: Code all intentional priority encoders using if-else-if statements. It is easier for
the typical design engineer to recognize a priority encoder when it is coded as an if-else-if
statement.