1) How to kill a process in fork/join?
The kill() task terminates the given process and all its sub-processes, that is, processes spawned using fork statements by the process being killed. If the process to be terminated is not blocked waiting on some other condition, such as an event, wait expression, or a delay then the process shall be terminated at some unspecified time in the current time step.
2) What is cross coverage ?
Cross allows keeping track of information which is received simultaneous on more than one cover point. Cross coverage is specified using the cross construct.
program main;
bit [0:1] y;
bit [0:1] y_values[$]= '{1,3};
bit [0:1] z;
bit [0:1] z_values[$]= '{1,2};
covergroup cg;
cover_point_y : coverpoint y ;
cover_point_z : coverpoint z ;
cross_yz : cross cover_point_y,cover_point_z ;
endgroup
cg cg_inst = new();
initial
foreach(y_values[i])
begin
y = y_values[i];
z = z_values[i];
cg_inst.sample();
end
endprogram
3) Why always block is not allowed in program block?
The program block does not allow always block. Only initial and methods are allowed, which are more controllable.
4) What is final block ?
SystemVerilog final blocks execute in an arbitrary but deterministic sequential order. This is possible because final blocks are limited to the legal set of statements allowed for functions.
EXAMPLE :
module fini;
initial
#100 $finish;
final
$display(" END OF SIMULATION at %d ",$time);
endmodule
RESULTS:
Wednesday, April 21, 2010
SystemVerilog Interview Questions 7
1) Difference between Associative array and Dynamic array ?
Answer:
Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically.
e.g. int array[];
When the size of the collection is unknown or the data space is sparse, an associative array is a better option. In associative array, it uses the transaction names as the keys in associative array.
e.g. int array[string];
2) What are the advantages of SystemVerilog DPI?
SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). The DPI provides a very simple, straightforward, and efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI.
3) What is bin?
A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions.
e.g.
program main;
bit [0:2] y;
bit [0:2] values[$]= '{3,5,6};
covergroup cg;
cover_point_y : coverpoint y
{ option.auto_bin_max = 4 ; }
endgroup
cg cg_inst = new();
initial
foreach(values[i])
begin
y = values[i];
cg_inst.sample();
end
endprogram
4) What are void functions ?
The function does not have return value
5) What is coverage driven verification?
Coverage Driven Verification is a result oriented approach to functional verification. The manager and verification terms define functional coverage points, and then work on the detail of process.
Used effectively coverage driven verification focuses the Verification team on measurable progress toward an agreed and comprehensive goal.
6) Explain about pass by ref and pass by value?
Pass by value is the default method through which arguments are passed into functions and tasks. Each subroutine retains a local copy of the argument. If the arguments are changed within the subroutine declaration, the changes do not affect the caller.
In pass by reference functions and tasks directly access the specified variables passed as arguments.Its like passing pointer of the variable.
example:
task pass(int i) // task pass(var int i) pass by reference
{
delay(10);
i = 1;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
delay(10);
i = 2;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
}
7) What is the difference between program block and module ?
The module is the basic building block in Verilog which works well for Design. However, for the testbench, a lot of effort is spent getting the environment properly initialized and synchronized, avoiding races between the design and the testbench, automating the generation of input stimuli, and reusing existing models and other infrastructure.
Systemverilog adds a new type of block called program block. Systemverilog adds a new type of block called program block. The program construct serves as a clear separator between design and testbench, and, more importantly, it specifies specialized execution semantics in the Reactive region for all elements declared within the program. Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench, and enables cycle and transaction level abstractions.
8) Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them.
Code Coverage indicates the how much of RTL has been exercised. The Functional Coverage indicates which features or functions has been executed. Both of them are very important. With only Code Coverage, it may not present the real features coverage. On the other hand, the functional coverage may miss some unused RTL coverage.
Answer:
Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically.
e.g. int array[];
When the size of the collection is unknown or the data space is sparse, an associative array is a better option. In associative array, it uses the transaction names as the keys in associative array.
e.g. int array[string];
2) What are the advantages of SystemVerilog DPI?
SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). The DPI provides a very simple, straightforward, and efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI.
3) What is bin?
A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions.
e.g.
program main;
bit [0:2] y;
bit [0:2] values[$]= '{3,5,6};
covergroup cg;
cover_point_y : coverpoint y
{ option.auto_bin_max = 4 ; }
endgroup
cg cg_inst = new();
initial
foreach(values[i])
begin
y = values[i];
cg_inst.sample();
end
endprogram
4) What are void functions ?
The function does not have return value
5) What is coverage driven verification?
Coverage Driven Verification is a result oriented approach to functional verification. The manager and verification terms define functional coverage points, and then work on the detail of process.
Used effectively coverage driven verification focuses the Verification team on measurable progress toward an agreed and comprehensive goal.
6) Explain about pass by ref and pass by value?
Pass by value is the default method through which arguments are passed into functions and tasks. Each subroutine retains a local copy of the argument. If the arguments are changed within the subroutine declaration, the changes do not affect the caller.
In pass by reference functions and tasks directly access the specified variables passed as arguments.Its like passing pointer of the variable.
example:
task pass(int i) // task pass(var int i) pass by reference
{
delay(10);
i = 1;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
delay(10);
i = 2;
printf(" i is changed to %d at %d\n",i,get_time(LO) );
}
7) What is the difference between program block and module ?
The module is the basic building block in Verilog which works well for Design. However, for the testbench, a lot of effort is spent getting the environment properly initialized and synchronized, avoiding races between the design and the testbench, automating the generation of input stimuli, and reusing existing models and other infrastructure.
Systemverilog adds a new type of block called program block. Systemverilog adds a new type of block called program block. The program construct serves as a clear separator between design and testbench, and, more importantly, it specifies specialized execution semantics in the Reactive region for all elements declared within the program. Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench, and enables cycle and transaction level abstractions.
8) Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them.
Code Coverage indicates the how much of RTL has been exercised. The Functional Coverage indicates which features or functions has been executed. Both of them are very important. With only Code Coverage, it may not present the real features coverage. On the other hand, the functional coverage may miss some unused RTL coverage.
SystemVerilog Interview Questions 6
1) What is the difference between $random and $urandom?
Answer:
The functionality of the seed arguments are different for $random and $urandom. The seed argument to $random is an inout. It updates its seed argument after each call to $random. This means the internal random number generator (RNG) state variable is a 32-bit number.
The seed argument to $urandom is an input. This seed is used to set the internal RNG to a value that is over 32-bits (typically 96-bits or greater).
In SystemVerilog, each thread has its own RNG, so only use the the seed argument on the first call to $urandom in each thread. There is also a way to set the seed without generated a random value by using the built-in process class and using the srandom() method.
class packet;
rand bit [7:0] header;
function new(int seed);
this.srandom(seed);
endfunction
endclass
initial begin
packet p=new;
p.new(33);
end
2) How do we get seed or use single seed in the VMM ?
Method 1: Let it random by itself
In VMM , VCS usually prints it to log file. Recently it added a system task to get the seed, something like: $get_initial_random_seed()
Use the following command to put seed back to get the same result "+nbt_random_seed=".
Method: Fix the seed.
The better approach is to use srandom task/function to fix the seed. We can increase the seed by 1 or use other script to generate the seed. The start seed is only start the regression. It has enough randomize with the test environment.
EXAMPLE:
class Rand_seed;
rand integer Var;
function new (int seed);
srandom(seed);
$display(" SEED is initised to %0d ",seed);
endfunction
function void post_randomize();
$display(": %0d :",Var);
endfunction
endclass
program Rand_seed_p_80;
Rand_seed rs;
initial
begin
rs = new(20);
repeat(5)
void'(rs.randomize());
rs = new(1);
repeat(5)
void'(rs.randomize());
rs = new(20);
repeat(5)
void'(rs.randomize());
end
endprogram
Answer:
The functionality of the seed arguments are different for $random and $urandom. The seed argument to $random is an inout. It updates its seed argument after each call to $random. This means the internal random number generator (RNG) state variable is a 32-bit number.
The seed argument to $urandom is an input. This seed is used to set the internal RNG to a value that is over 32-bits (typically 96-bits or greater).
In SystemVerilog, each thread has its own RNG, so only use the the seed argument on the first call to $urandom in each thread. There is also a way to set the seed without generated a random value by using the built-in process class and using the srandom() method.
class packet;
rand bit [7:0] header;
function new(int seed);
this.srandom(seed);
endfunction
endclass
initial begin
packet p=new;
p.new(33);
end
2) How do we get seed or use single seed in the VMM ?
Method 1: Let it random by itself
In VMM , VCS usually prints it to log file. Recently it added a system task to get the seed, something like: $get_initial_random_seed()
Use the following command to put seed back to get the same result "+nbt_random_seed=
Method: Fix the seed.
The better approach is to use srandom task/function to fix the seed. We can increase the seed by 1 or use other script to generate the seed. The start seed is only start the regression. It has enough randomize with the test environment.
EXAMPLE:
class Rand_seed;
rand integer Var;
function new (int seed);
srandom(seed);
$display(" SEED is initised to %0d ",seed);
endfunction
function void post_randomize();
$display(": %0d :",Var);
endfunction
endclass
program Rand_seed_p_80;
Rand_seed rs;
initial
begin
rs = new(20);
repeat(5)
void'(rs.randomize());
rs = new(1);
repeat(5)
void'(rs.randomize());
rs = new(20);
repeat(5)
void'(rs.randomize());
end
endprogram
SystemVerilog Interview Question 5
1) What is the use of modports ?
Answer:
Modport restrict interface access within a module based on the direction declared. Directions of signals are specified as seen from the module.
e.g.
interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;
modport dut (input read,enable,addr,output data);
modport tb (output read,enable,addr,input data);
endinterface :intf
2) How parallel case and full cases problems are avoided in SV?
The full_case and parallel_case directives are dangerous because they tell the synthesis tool
something different about the design than what is told to the simulator.
To the Verilog simulator, full_case and parallel_case are buried inside of Verilog
comments and are completely ignored. To the synthesis tool, full_case and parallel_case
are command-directives that instruct the synthesis tools to potentially take certain actions or
perform certain optimizations that are unknown to the simulator.
A full case statement is a case statement in which all possible case-expression binary patterns
can be matched to a case item or to a case default.
e.g. Full case, sel=2'b11 will be covered by default statement.
The x-assignment will also be treated as a don'tcare for synthesis, which may allow the synthesis tool to further optimize the synthesized design. It's the potentially causing a mismatch to occur between simulation and synthesis. To insure that the pre-synthesis and post-synthesis simulations match, the case default could assign the y-output to either a
predetermined constant value, or to one of the other multiplexer input values
module mux3c
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule
// Use synopsys full_case statement to create the full case , but it treated differently in simulation and synthesis.
module mux3b (y, a, b, c, sel);
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel) // synopsys full_case
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
endcase
endmodule
SystemVerilog use priority modified case statement to solve the full case problem.
The biggest difference between a full_case directive and a priority modified case statement
is that the priority keyword is part of the SystemVerilog syntax that will be interpreted the
same by simulators, synthesis tools and formal verification tools. In essence, the priority case
statement is a "safe" full_case case statement.
e.g.
priority case (...)
...
endcase
A parallel case statement is a case statement in which it is only possible to match any case
expression to one and only one case item.
e.g. A parallel case statement
module intctl1b
(output reg int2, int1, int0,
input [2:0] irq );
always @* begin
{int2, int1, int0} = 3'b0;
casez (irq) // synopsys parallel_case
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule
This is an example that demonstrates that adding the parallel_case directive makes the design
smaller and faster, but in the process it also adversely changes the functionality of the design.
SystemVerilog adds the new case statement modifier called "unique."
The unique keyword shall cause the simulator to report a run-time error if a case expression is
ever found to match more than one of the case items. In essence, the unique
case statement is a "safe" parallel_case case statement.
unique case (...)
...
default: ...
endcase
Guideline: Code all intentional priority encoders using if-else-if statements. It is easier for
the typical design engineer to recognize a priority encoder when it is coded as an if-else-if
statement.
Answer:
Modport restrict interface access within a module based on the direction declared. Directions of signals are specified as seen from the module.
e.g.
interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;
modport dut (input read,enable,addr,output data);
modport tb (output read,enable,addr,input data);
endinterface :intf
2) How parallel case and full cases problems are avoided in SV?
The full_case and parallel_case directives are dangerous because they tell the synthesis tool
something different about the design than what is told to the simulator.
To the Verilog simulator, full_case and parallel_case are buried inside of Verilog
comments and are completely ignored. To the synthesis tool, full_case and parallel_case
are command-directives that instruct the synthesis tools to potentially take certain actions or
perform certain optimizations that are unknown to the simulator.
A full case statement is a case statement in which all possible case-expression binary patterns
can be matched to a case item or to a case default.
e.g. Full case, sel=2'b11 will be covered by default statement.
The x-assignment will also be treated as a don'tcare for synthesis, which may allow the synthesis tool to further optimize the synthesized design. It's the potentially causing a mismatch to occur between simulation and synthesis. To insure that the pre-synthesis and post-synthesis simulations match, the case default could assign the y-output to either a
predetermined constant value, or to one of the other multiplexer input values
module mux3c
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule
// Use synopsys full_case statement to create the full case , but it treated differently in simulation and synthesis.
module mux3b (y, a, b, c, sel);
(output reg y,
input [1:0] sel,
input a, b, c);
always @*
case (sel) // synopsys full_case
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
endcase
endmodule
SystemVerilog use priority modified case statement to solve the full case problem.
The biggest difference between a full_case directive and a priority modified case statement
is that the priority keyword is part of the SystemVerilog syntax that will be interpreted the
same by simulators, synthesis tools and formal verification tools. In essence, the priority case
statement is a "safe" full_case case statement.
e.g.
priority case (...)
...
endcase
A parallel case statement is a case statement in which it is only possible to match any case
expression to one and only one case item.
e.g. A parallel case statement
module intctl1b
(output reg int2, int1, int0,
input [2:0] irq );
always @* begin
{int2, int1, int0} = 3'b0;
casez (irq) // synopsys parallel_case
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule
This is an example that demonstrates that adding the parallel_case directive makes the design
smaller and faster, but in the process it also adversely changes the functionality of the design.
SystemVerilog adds the new case statement modifier called "unique."
The unique keyword shall cause the simulator to report a run-time error if a case expression is
ever found to match more than one of the case items. In essence, the unique
case statement is a "safe" parallel_case case statement.
unique case (...)
...
default: ...
endcase
Guideline: Code all intentional priority encoders using if-else-if statements. It is easier for
the typical design engineer to recognize a priority encoder when it is coded as an if-else-if
statement.
SystemVerilog interview Questions 4
1) How to call the task which is defined in parent object into derived class ?
Answer:
The super keyword is used from within a derived class to refer to members of the parent class. It is necessary to use super to access members of a parent class when those members are overridden by the derived class.
EXAMPLE:
class parent;
task printf();
$display(" THIS IS PARENT CLASS ");
endtask
endclass
class subclass extends parent;
task printf();
super.printf();
endtask
endclass
program main;
initial
begin
subclass s;
s = new();
s.printf();
end
endprogram
RESULT
THIS IS PARENT CLASS
2) What is the difference between rand and randc?
Answer:
rand are standard random variables. When there are no other control on distrubution, these variables are uniformly distributed across valid values.
randc are random cyclic that randomly iterates over all the values in the range and no value is repeated with in an iteration until every possible value has been assigned.
3) What is solve...before constraint ?
Answer:
constraint order { solve a before b ;}
This guides the solver to give highest priority to a than b while picking the solution from solution space.
Answer:
4) What is the difference between fork/joins, fork/join_none fork/join_any ?
Fork Join None: The parent process continues to execute concurrently with all the processes spawned by the fork. The spawned processes do not start executing until the parent thread executes a blocking statement.
Fork Join Any: The parent process blocks until any one of the processes spawned by this fork completes.
For Join All: The parent process blocks until all the processes spawned by this fork complete.
Answer:
The super keyword is used from within a derived class to refer to members of the parent class. It is necessary to use super to access members of a parent class when those members are overridden by the derived class.
EXAMPLE:
class parent;
task printf();
$display(" THIS IS PARENT CLASS ");
endtask
endclass
class subclass extends parent;
task printf();
super.printf();
endtask
endclass
program main;
initial
begin
subclass s;
s = new();
s.printf();
end
endprogram
RESULT
THIS IS PARENT CLASS
2) What is the difference between rand and randc?
Answer:
rand are standard random variables. When there are no other control on distrubution, these variables are uniformly distributed across valid values.
randc are random cyclic that randomly iterates over all the values in the range and no value is repeated with in an iteration until every possible value has been assigned.
3) What is solve...before constraint ?
Answer:
constraint order { solve a before b ;}
This guides the solver to give highest priority to a than b while picking the solution from solution space.
Answer:
4) What is the difference between fork/joins, fork/join_none fork/join_any ?
Fork Join None: The parent process continues to execute concurrently with all the processes spawned by the fork. The spawned processes do not start executing until the parent thread executes a blocking statement.
Fork Join Any: The parent process blocks until any one of the processes spawned by this fork completes.
For Join All: The parent process blocks until all the processes spawned by this fork complete.
Systemverilog Interview Questions 3
1) What is the difference between mailbox and queue?
Answer:
A queue is a variable-size, ordered collection of homogeneous elements. A Queue is analogous to one dimensional unpacked array that grows and shrinks automatically. Queues can be used to model a last in, first out buffer or first in, first out buffer.
// Other data type as reference
// int q[]; dynamic array
// int q[5]; fixed array
// int q[string]; associate array
// include <
// List#(integer) List1; //
int q[$] = { 2, 4, 8 };
int p[$];
int e, pos;
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q[0] = e; // write the first item
p = q; // read and write entire queue (copy)
A mailbox is a communication mechanism that allows messages to be exchanged between processes. Data can be sent to a mailbox by one process and retrieved by another.
2) What data structure you used to build scoreboard?
Answer:
In SV, we use mailbox to get data from different modules and compare the result.
class Scoreboard;
mailbox drvr2sb;
mailbox rcvr2sb;
function new(mailbox drvr2sb,mailbox rcvr2sb);
this.drvr2sb = drvr2sb;
this.rcvr2sb = rcvr2sb;
endfunction:new
task start();
packet pkt_rcv,pkt_exp;
forever
begin
rcvr2sb.get(pkt_rcv);
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time);
drvr2sb.get(pkt_exp);
if(pkt_rcv.compare(pkt_exp))
$display(" %0d : Scoreboardd :Packet Matched ",$time);
else
$root.error++;
end
endtask : start
endclass
In VMM, we use channels to connect all the modules and compare the result.
class Scoreboard extends vmm_xactor;
Packet_channel drvr2sb_chan;
Packet_channel rcvr2sb_chan;
function new(string inst = "class",
int unsigned stream_id = -1,
Packet_channel drvr2sb_chan = null,
Packet_channel rcvr2sb_chan = null);
super.new("sb",inst,stream_id);
if(drvr2sb_chan == null)
`vmm_fatal(this.log,"drvr2sb_channel is not constructed");
else
this.drvr2sb_chan = drvr2sb_chan;
if(rcvr2sb_chan == null)
`vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
else
this.rcvr2sb_chan = rcvr2sb_chan;
`vmm_note(log,"Scoreboard created ");
endfunction:new
task main();
Packet pkt_rcv,pkt_exp;
string msg;
super.main();
forever
begin
rcvr2sb_chan.get(pkt_rcv);
$display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time);
drvr2sb_chan.get(pkt_exp);
if(pkt_rcv.compare(pkt_exp,msg))
$display(" %0d : Scoreboard :Packet Matched ",$time);
else
`vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg));
end
endtask : main
endclass
3) What are the advantages of linkedlist over the queue ?
Answer:
Queue has a certain order. It's hard to insert the data within the queue. But Linkedlist can easily insert the data in any location.
4) What is the use of $cast?
Using Casting one can assign values to variables that might not ordinarily be valid because of differing data type. SystemVerilog adds 2 types of casting. Static casting and dynamic casting.
e.g. i = int '(10.0-0.1); // static cast convert real to integer
// Dynamic casting
function int $cast( singular dest_var, singular source_exp );
or
task $cast( singular dest_var, singular source_exp );
e.g. $cast( col, 2 + 3 );
Answer:
A queue is a variable-size, ordered collection of homogeneous elements. A Queue is analogous to one dimensional unpacked array that grows and shrinks automatically. Queues can be used to model a last in, first out buffer or first in, first out buffer.
// Other data type as reference
// int q[]; dynamic array
// int q[5]; fixed array
// int q[string]; associate array
// include <
// List#(integer) List1; //
int q[$] = { 2, 4, 8 };
int p[$];
int e, pos;
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q[0] = e; // write the first item
p = q; // read and write entire queue (copy)
mailbox drvr2sb;
mailbox rcvr2sb;
function new(mailbox drvr2sb,mailbox rcvr2sb);
this.drvr2sb = drvr2sb;
this.rcvr2sb = rcvr2sb;
endfunction:new
task start();
packet pkt_rcv,pkt_exp;
forever
begin
rcvr2sb.get(pkt_rcv);
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time);
drvr2sb.get(pkt_exp);
if(pkt_rcv.compare(pkt_exp))
$display(" %0d : Scoreboardd :Packet Matched ",$time);
else
$root.error++;
end
endtask : start
endclass
In VMM, we use channels to connect all the modules and compare the result.
Packet_channel drvr2sb_chan;
Packet_channel rcvr2sb_chan;
function new(string inst = "class",
int unsigned stream_id = -1,
Packet_channel drvr2sb_chan = null,
Packet_channel rcvr2sb_chan = null);
super.new("sb",inst,stream_id);
if(drvr2sb_chan == null)
`vmm_fatal(this.log,"drvr2sb_channel is not constructed");
else
this.drvr2sb_chan = drvr2sb_chan;
if(rcvr2sb_chan == null)
`vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
else
this.rcvr2sb_chan = rcvr2sb_chan;
`vmm_note(log,"Scoreboard created ");
endfunction:new
task main();
Packet pkt_rcv,pkt_exp;
string msg;
super.main();
forever
begin
rcvr2sb_chan.get(pkt_rcv);
$display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time);
drvr2sb_chan.get(pkt_exp);
if(pkt_rcv.compare(pkt_exp,msg))
$display(" %0d : Scoreboard :Packet Matched ",$time);
else
`vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg));
end
endtask : main
endclass
or
task $cast( singular dest_var, singular source_exp );
ASIC Verification Interview Questions
1) What if design engineer and verification engineer do the same mistake in Test bench BFM(Bus Functional Model) and RTL(DUT)? How can you able to detect errors?
Answer: 1. Code reviews & protocol checkers
2. IP gets verified in multiple environments .. like block level test bench, out of box testbench (connecting DUT back to back) , full fledged testbench using proven BFM, SoC level testbench using processor and all that etc... this all environments SHOULD be executed by diferent persons and so you should be able to catch that bug in one of this testbench ...
3. customer will catch the problem ( worst case )
2) If you got a failure from the customer, how do you debug this? How do you prevent it to happen again?
Answer: 1. First, try to reproduce the problem in your own environment. Try to get customer's vector, so you can inject the same vector to create the problem in house.
2. If you confirm the problem and fix them, you should put the new assertion or test to catch the problem again. Add this new test in the future test plan, so the problem will not happen again.
Answer: 1. Code reviews & protocol checkers
2. IP gets verified in multiple environments .. like block level test bench, out of box testbench (connecting DUT back to back) , full fledged testbench using proven BFM, SoC level testbench using processor and all that etc... this all environments SHOULD be executed by diferent persons and so you should be able to catch that bug in one of this testbench ...
3. customer will catch the problem ( worst case )
2) If you got a failure from the customer, how do you debug this? How do you prevent it to happen again?
Answer: 1. First, try to reproduce the problem in your own environment. Try to get customer's vector, so you can inject the same vector to create the problem in house.
2. If you confirm the problem and fix them, you should put the new assertion or test to catch the problem again. Add this new test in the future test plan, so the problem will not happen again.
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