module Stack (DataIO, Reset, Push, Pop, SP, Full, Empty, Err);
//Verilog code for stack
/* declare input, output and inout ports */
inout [3:0] DataIO;
input Push,Pop,Reset;
output Empty,Err;
Full,output [2:0] SP; // Stack pointer
// declare registers
regEmpty,Err;
Full,reg [2:0] SP;
reg [3:0] Stack[7:0];
reg [3:0] DataR;
/* continuous assignment of DataIO to DataR register, with delay 0 */
wire [3:0] #(0) DataIO = DataR;
// put DataR in high impedance, so the stack can get data
always @ (negedge Pop)
begin
DataR = 4'bzzzz;
end
always @ (posedge Push or posedge Pop or posedge Reset)
begin
if (Reset==1)
begin
DataR = 4'bzzzz;
SP = 3'b0;
Full = 0;
Empty = 0;
Err = 0;
end
if (Push==1) begin
//when the stack is empty
if (Empty==1)
begin
Stack[SP] = DataIO;
Empty = 0;
if (Err==1)
Err=0;
end
else // when the stack is full
if(full==1)
begin
Stack[SP] = DataIO;
Err = 1;
end
else
begin
SP = SP +1;
Stack [SP] = DataIO;
if (SP == 3'b111)
Full = 1;
end
end // end of push
if(Pop==1) begin
/* if SP indicates the last location but the stack is not empty */
if ((SP == 3'b000) && (Empty!=1)
begin
DataR = Stack[SP];
Empty = 1;
end
else // if the stack is emtpy
if(Empty==1)
begin
DataR = Stack[SP];
Err = 1;
end
else
begin
DataR = Stack[SP];
if (SP != 3'b000)
SP = SP-1;
// if the stack is full
if (Err==1) Err = 0;
if (Full==1) Full = 0;
end
end // end of pop
end // end of always loop
endmodule
2) what is difference between CAM and TCAM?
First, CAM stands for Content Addressable Memory. A CAM is a special type of memory; some would say the opposite of RAM. With normal computer memory (RAM) the operating system provides an address, and receives the data stored at the supplied address. With a CAM, the operating system supplies the data, and the CAM returns a list of addresses where the data is stored, if it finds any. Furthermore, a CAM searches the entire memory in one operation, so it is considerably faster than RAM.
The most commonly implemented CAMs are called binary CAMs. They search only for ones and zeros; a simple operation. MAC address tables in switches commonly get stored inside binary CAMs. With CAMs, the operating system can find what it needs in a single operation. In this case it's the switchport that data should be sent out, based on the given MAC address,
The TCAM is a Ternary CAM. This allows the operating system to match a third state, "X." The X state is a "mask," meaning its value can be anything. This lends itself well to networking, since netmasks (define) operate this way. To calculate a subnet address we mask the bits we don't care about, and then apply the logical AND operation to the rest. Routers can store their entire routing table in these TCAMs, allowing for very quick lookups.
3) One-hot state machine vs highly encoded state machine
Answer:
One-hot state machine: better performance, easy encode
highly encode state machine has less bit for state parameters
e.g.
Using Single Always For Sequential, Combo And Output Logic
//==================================================== 2 // This is FSM demo program using single always 3 // for both seq and combo logic 4 // Design Name : fsm_using_single_always 5 // File Name : fsm_using_single_always.v 6 //===================================================== 7 module fsm_using_single_always (
8 clock , // clock 9 reset , // Active high, syn reset 10 req_0 , // Request 0 11 req_1 , // Request 1 12 gnt_0 , // Grant 0 13 gnt_1
14 );
15 //=============Input Ports============================= 16 input clock,reset,req_0,req_1;
17 //=============Output Ports=========================== 18 output gnt_0,gnt_1;
19 //=============Input ports Data Type=================== 20 wire clock,reset,req_0,req_1;
21 //=============Output Ports Data Type================== 22 reg gnt_0,gnt_1;
23 //=============Internal Constants====================== 24 parameter SIZE = 3 ;
25 parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
26 //=============Internal Variables====================== 27 reg [SIZE-1:0] state ;// Seq part of the FSM 28 reg [SIZE-1:0] next_state ;// combo part of FSM 29 //==========Code startes Here========================== 30 always @ (posedge clock)
31 begin : FSM
32 if (reset == 1'b1) begin
33 state <= #1 IDLE;
34 gnt_0 <= 0;
35 gnt_1 <= 0;
36 end else
37 case(state)
38 IDLE : if (req_0 == 1'b1) begin
39 state <= #1 GNT0;
40 gnt_0 <= 1;
41 end else if (req_1 == 1'b1) begin
42 gnt_1 <= 1;
43 state <= #1 GNT1;
44 end else begin
45 state <= #1 IDLE;
46 end
47 GNT0 : if (req_0 == 1'b1) begin
48 state <= #1 GNT0;
49 end else begin
50 gnt_0 <= 0;
51 state <= #1 IDLE;
52 end
53 GNT1 : if (req_1 == 1'b1) begin
54 state <= #1 GNT1;
55 end else begin
56 gnt_1 <= 0;
57 state <= #1 IDLE;
58 end
59 default : state <= #1 IDLE;
60 endcase
61 end
62
63 endmodule // End of Module arbiter
4) Write a perl script to read a file and then count the "ERROR=number" ? Check the number did increase.
Answer:
First, you can use grep -f patternfile source > target to generate a new log file with ERROR=# format or directly use perl to do it.
Assume the log file has the format "ERROR=number" format in some lines,
#!/usr/bin/perl
system(grep "ERROR" logfile > error_logfile);
open(IN, "error_logfile") or die "Cannot open the error_logfile!";
while($line=
chop($line);
@err_array = split(/\d/,$line);
$w=1;
while ($$w<= @err_array) {
if($err_array[$w-1] < $err_array[$w])
{ $err_incr_cnt +=1;
}
else
{ $err_decr_cnt +=1;
}
$w++;
}
}
print "Total number of error = $w";
print "Error Increment counter = $err_incr_cnt";
print "Error Decrement counter =$err_decr_cnt;
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