ASIC Gate Interview Questions Part #1

Here are the basic interview questions and answer from my previous experience and other source.

1) What is the difference between a latch and a flip lop. For the same input, how would the output look for a latch and for a flip-flop.

Latch is a level-sensitive "sequential" element. The output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

It's faster than Flip-flop, it takes less gates to implemented ( less area). But it's sensitive to glitches on enable pin. It also can be clocked or clock less.

Flip-flop is a edge sensitive "sequential" element. Flip flop will store the input only when there is a rising or falling edge of the clock.

FF is immune to glitches. D-FF is built from two latches. They are in master slave configuration.

2) What's finite state machines?

A finite state machine(FSM), is a model of behavior composed of a finite number of states, transitions between those states, and actions. It is similar to a "flow graph" where we can inspect the way in which the logic runs when certain conditions are met.
They are two types of FSM. Mealy Machine and Moore Machine:

Moore Machines uses only entry actions and output depends on the state.

Mealy Machines uses only input actions and output depends on the input and the state.

For more detail, please check this link


3) Explain the differences between "direct Mapped", "fully Associative" and "Set Associative" caches.

Answer:
If each block has only one place it can appear in the cache, the cache
is said to be direct mapped. The mapping is usually (block-frame address)
modulo (number of blocks in cache).

If a block can be placed anywhere in the cache, the cache is said to be
fully associative.

If a block can be placed in a restricted set of places in the cache, the cache
is said to be set associative. A set is a group of two or more
blocks in the cache. A block is first mapped onto a set, and then the block
can be placed anywhere within the set. The set is usually chosen by bit
selection; that is, (block-frame address) modulo (number of sets in cache).
If there are n blocks in a set, the cache placement is
called n-way set associative.


4) Design a four-input NAND gate using only two-input NAND gates.
 


Answer:

Tie the inputs of NAND gate together to get an inverter. The result is as following: