System Verilog Interview Questions 2

1) What's the OpenVera?

Its an intuitive, easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java with additional constructs targeted at functional verification that makes it ideal for developing testbenches, assertions and properties.
   
2) What is SVA?

Answer: SVA is System Verilog Assertion.

3) What is Callback?

Callback in system verilog or verification : Callback is mechanism of changing to behavior of a verification component such as driver or generator or monitor without actually changing to code of the component.
It's used for functional coverage, inject error and output transaction in a scoreboard.

4) What is "factory pattern" concept?

The term factory method is often used to refer to any method whose main purpose is creation of objects.

e.g.

// Normal Type based object creation

// Class object

class my_class;

   int i;

endclass


program main;

   // Create object type my_class

   my_class obj1;

   obj1 = new

endprogram


 

// Using Factory I should be able to do the following

program main;

   base_class my_class_object;   

   base_class = factory.create_object("my_class"); // See here the type of the object to be created is passed as a string so we dont know the exact type of the object

endprogram

5) What's the difference between data type logic, reg and wire?

Data Type	Wire	Reg	Logic
Assignments	Continuous assignments	blocking/non blocking assignment	Both continuous assignment or blocking/non blocking assignment
Limitation	Wire, cannot hold data	Storage element, store data until next assignment	extends the rand eg type so it can be driven by a single driver such as gate or module.

6) What is the need of clocking blocks?

- It is used to specify synchronization characteristics of the design
- It Offers a clean way to drive and sample signals
- Provides race-free operation if input skew > 0
- Helps in testbench driving the signals at the right time
-  Features
    - Clock specification
    - Input skew,output skew
    - Cycle delay (##)
- Can be declared inside interface,module or program

e.g.

Module M1(ck, enin, din, enout, dout);
input ck,enin;
input [31:0] din ;
output enout ;
output [31:0] dout ;

clocking sd @(posedge ck);
input #2ns ein,din ;
output #3ns enout, dout;
endclocking:sd

reg [7:0] sab ;
initial begin
sab = sd.din[7:0];
end
endmodule:M1



7) What are the ways to avoid race condition between testbench and RTL using SystemVerilog?

There are mainly following ways to avoid the race condition between testbench and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

According to the eRM and OVM monitors and drivers should always be completely separate. This approach was adopted mainly in order to facilitate reuse of block level agents in a top level testbench: at block level both driver and monitor are used, while at top level only the monitor is used.




8)  Explain Event regions in SV?

 A systemverilog event is now a handle to a synchronization object that can be passed around to routines. The events can be shared across objects without having to make the events global.

9) What are the types of coverages available in SV?



Both Code Coverage and Functional Coverage are available in SV. You can use the following examples:

Using covergroup : variables, expression, and their cross
Using cover keyword : properties

class eth_frame;

// Definitions as above
covergroup cov;
coverpoint dest {
bins bcast[1] = {48'hFFFFFFFFFFFF};
bins ucast[1] = default;
}
coverpoint type {
bins length[16] = { [0:1535] };
bins typed[16] = { [1536:32767] };
bins other[1] = default;
}
psize: coverpoint payload.size {
bins size[] = { 46, [47:63], 64, [65:511], [512:1023], [1024:1499], 1500 };
}

sz_x_t: cross type, psize;
endgroup
endclass

module Amod2(input bit clk);
bit X, Y;
sequence s1;
@(posedge clk) X ##1 Y;
endsequence
CovLavel: cover property (s1);
...
endmodule