Clock Domain Crossing Timing Q&A

1) What are the major issues for Clock Domain Crossing ?

Answers:

They are 3 major problems for clock domain crossing:

 A. Metastability - the transaction of data violated the setup or hold time of the destination FF. It caused the ouput may oscillate for an indefinite amount time.  
      The Metastability may lead to the high current or even burn out of the chip. It also caused functional issue and timing issue.


B. Data Loss - whenever a new source data is generated, it may not be captured by the destination domain in the very first cycle of the destination clock because of metastability. Plus the different clock frequency of source and destination  may also caused the data loss.



C. Data Incoherency - whenever new data is generated in the source clock domain, it may take 1 or more destination clock cycles to capture it, depending on the arrival time of active clock edges.  


Solutions:

There are 4 common method to solve the clock domains crossing problems:

1.  MUX recirculation technique





The MUX recirculation technique is shown as below:

A control signal EN, generated in the source domain is synchronized in the destination domain using a multi-flop synchronizer. The synchronized control signal EN_Sync drives the select pin of the muxes, thereby controlling the data transfer for all bits of the bus A. In this way, individual bits of the bus are not synchronized separately, and hence there is no data incoherency. However, it is important to ensure that when the control signal is active, the source domain data A[0:1] should be held constant.

     
 2. Handshake synchronization



A very common and robust method for synchronizing multiple data signals is a handshake technique as shown in Figure. This is popular because the handshake technique can easily manage changes in clock frequencies, while minimizing latency at the crossing.

3.  FIFO synchronization
FIFO is used when you need to transfer data from one clock domain (clock domain at which you store data) to another clock domain, it grantees that the data will cross from that domain to the other (smoothly) if the Asynchronous FIFO is designed right (Async FIFO usually will include Synchronizers or similar approaches) FIFO will introduce latency to assure that the data crosses the domain approriately


4. Multi-Flop Synchronizer

The synchronizers allow sufficient time for the oscillations to settle down and ensure that a stable output is obtained in the destination domain. A commonly used synchronizer is a multi-flop synchronizer as shown in