Answer:
In the blocking statement, the RHS will be evaluated and the LHS will be then updated without any interruptions.
In the non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS will be updated at the end of the time step. Within the whole period, the other process can run in parallel.
2) How do you model a synchronous and asynchronous reset in Verilog?
Answer:
Synchronous reset:
always @(posedge clk)
begin
----
if (reset)
begin
-----
end
end
Asynchronous reset:
always @(posedge clk or negedge reset)
begin
-----
if (!reset)
begin
-----
end
end
In asynchronous reset, the always block will invoked at the negative edge of the reset signal, irrespective of clock's value.
3) What happens if there is connecting wires width mismatch?
Answer:
For examples:
RHS[7:0] = LHS[15:0]
The end result is LHS[7:0] = RHS[7:0];
The assignments starts from LSBs of the signals, and ends at the MSB of smaller width signal.
4) What are different options that can be used with $display statement in Verilog?
%b - binary
%c - ASCII character
%d - Decimal
%h - Hexadecimal
%m - Hierarchical name
%o - Octal
%s - Steing
%t - Time
%v - Net signal strength
5) Give the precedence order of the operators in Verilog.
Answer:
6) Should we include all the inputs of a combinational circuit in the sensitivity lists? Give reason.
Answer:
Yes, in combinational circuit all inputs should be included in the sensitivity lists, otherwise, it will result in a synthesis error.
7) What is the difference between a task and a function in verilog?
Answer:
Function | Task | |
Time-Control statements | No, shall execute in one simulation time unit | Yes |
Call function or tasks | Cannot call tasks | Can call both tasks and functions |
input type argument | at least 1 input type argument and shall not have an output or inout type argument | can have 0 or more arguments of any type |
return value | return a single value | shall not return a value |
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