Verilog Interview Questions Part #3

1) What is the difference between the following two lines of verilog code?

#5 a=b;
a= #5 b;

Answer:
#5 a=b; Wait 5 time units before doing the action for "a=b".

a= #5 b; The value of b is calculated and stored in an internal temp register. After 5 time units, assign this stored value to a.


2) What is the difference between

c foo ? a:b;

and

if(foo) c=a; else c=b;

Answer:

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a=2'b10 and b=2'b11,
you'd get c=2'b1x.

On the other hand, if treats Xs and Zs as FALSE, so you'd always get c=b.

3) what's difference between $monitor and $display?

Answer:

$monitor: display every time one of it's parameters change.
$display : display once every time they are executed.
$strobe: display only at the end of the current simulation time

4) What's the different between casex, casez and case statements?

Answer:

casez treats all z as "Don't care".
casex treat all z or x as "Don't care".
case pass all z or x to the result.

Example:
Driving 0
Normal : Logic 0 on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel

Driving 1
Normal : Logic 1 on sel
CASEX : Logic 1 on sel
CASEZ : Logic 1 on sel

Driving x
Normal : Logic x on sel
CASEX : Logic 0 on sel
CASEZ : Logic x on sel

Driving z
Normal : Logic z on sel
CASEX : Logic 0 on sel
CASEZ : Logic 0 on sel


5) What's the differenece between wire and reg data type?

Answer:

Wire is a net data type, represents connections between hardware elements. It's default value is z.
Reg is a register data type, which represent data storage elements. Registers retain value until another value is placed onto them. It's default value is x.
e reg.


6) What is defparam used for?

Answer:

Defparam is used to pass a new set of parameters during instantiation

For example:

1 module secret_number;
2 parameter my_secret = 0;
3
4 initial begin
5 $display("My secret number is %d", my_secret);
6 end
7
8 endmodule
9
10 module defparam_example();
11
12 defparam U0.my_secret = 11;
13 defparam U1.my_secret = 22;
14
15 secret_number U0();
16 secret_number U1();
17
18 endmodule