Verilog Interview Questions Part #2

1) Given the following Verilog Code, what value of a "a" is displayed?

always @(clk) begin
a = 0;
a <= 1; $display(a); end Answer: Verilog scheduling semantics basically imply a 4 level deep queue for the current simulation time: 1: Active Evens ( blocking statements) 2: Inactive Events ( #0 delays, etc) 3: Non-Blocking Assign updates ( non-blocking statements ) 4: Monitor Events ($display, $monitor, etc ). Since the "a=0" is an active event, it's scheduled into the 1st "queue". The "a<= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle: 1st sim cycle: a=0, display show a=0; 2nd sim cycle: display a =1; 2)

Show the waveform of the following code:

always @(a) begin #10 ( same as blocking statement ) b1 =a; end

always@(a) begin b2 = #10 a; ( #10 as the delay ) end

Answer:

always @(a) begin #10 ( same as blocking statement ) b1 =a; end	always@(a) begin b2 = #10 a; ( #10 as the delay ) end
a ====____________________ b1 _______________________ t =0, t=10ns at t=10ns, b1 = a;	a ===_____________________ b1 ______________===______ t =0, t=10ns Read a at time t=0, assign the b2 =a at 10ns

2) Given the following snipet of Verilog code, draw out the waveforms for clk and a

always @(clk)
begin
a=0;
#5 a=1;
end


Answer:

You should add the always@(posedge clk), otherwise, the result will be unstable.

10 30 50 70 90
clk ___===___===___===___===___===___

a __________________===__________