Verilog Interview Questions Part #4

1) Write code for 2:1 MUX using different coding methods?

Use assign statement:

7 module mux_using_assign(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports---------------
14 input din_0, din_1, sel ;
15 //-----------Output Ports---------------
16 output mux_out;
17 //------------Internal Variables--------
18 wire mux_out;
19 //-------------Code Start-----------------
20 assign mux_out = (sel) ? din_1 : din_0;
21
22 endmodule //End Of Module mux

Use if statement
7 module mux_using_if(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports---------------
14 input din_0, din_1, sel ;
15 //-----------Output Ports---------------
16 output mux_out;
17 //------------Internal Variables--------
18 reg mux_out;
19 //-------------Code Starts Here---------
20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 if (sel == 1'b0) begin
23 mux_out = din_0;
24 end else begin
25 mux_out = din_1 ;
26 end
27 end
28
29 endmodule //End Of Module mux

Use Case statement
7 module mux_using_case(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports---------------
14 input din_0, din_1, sel ;
15 //-----------Output Ports---------------
16 output mux_out;
17 //------------Internal Variables--------
18 reg mux_out;
19 //-------------Code Starts Here---------
20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 case(sel )
23 1'b0 : mux_out = din_0;
24 1'b1 : mux_out = din_1;
25 endcase
26 end
27
28 endmodule //End Of Module mux





2) What's the difference between === and ==?

Answer:
"a===b" a equal to b, including x and z (Case equality)
"a==b" a equal to b, result may be unknown (logical equality)
The equality operators ( = = , ! = ) will yield an x if either operand
has x or z in its bits. Where as the case equality operators ( = = = ,
! = = ) compare both operands bit by bit and compare all bits,
including x and z.



3) Write code for a parallel encoder and a priority encoder?


module pri_encoder_using_assign (
8 binary_out , // 4 bit binary output
9 encoder_in , // 16-bit input
10 enable // Enable for the encoder
11 );
12
13 output [3:0] binary_out ;
14 input enable ;
15 input [15:0] encoder_in ;
16
17 wire [3:0] binary_out ;
18
19 assign binary_out = ( ! enable) ? 0 : (
20 (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
21 (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
22 (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
23 (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
24 (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
25 (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
26 (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
27 (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
28 (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
29 (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
30 (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
31 (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
32 (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
33 (encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
34 (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
35
36 endmodule

module encoder_using_case(
8 binary_out , // 4 bit binary Output
9 encoder_in , // 16-bit Input
10 enable // Enable for the encoder
11 );
12 output [3:0] binary_out ;
13 input enable ;
14 input [15:0] encoder_in ;
15
16 reg [3:0] binary_out ;
17
18 always @ (enable or encoder_in)
19 begin
20 binary_out = 0;
21 if (enable) begin
22 case (encoder_in)
23 16'h0002 : binary_out = 1;
24 16'h0004 : binary_out = 2;
25 16'h0008 : binary_out = 3;
26 16'h0010 : binary_out = 4;
27 16'h0020 : binary_out = 5;
28 16'h0040 : binary_out = 6;
29 16'h0080 : binary_out = 7;
30 16'h0100 : binary_out = 8;
31 16'h0200 : binary_out = 9;
32 16'h0400 : binary_out = 10;
33 16'h0800 : binary_out = 11;
34 16'h1000 : binary_out = 12;
35 16'h2000 : binary_out = 13;
36 16'h4000 : binary_out = 14;
37 16'h8000 : binary_out = 15;
38 endcase
39 end
40 end
41
42 endmodule