ASIC Timing Interview Questions

1)



The digital circuit is shown with logic delay (dly3) and two clock buffer delays (dly1, dly2).

How will you fix setup timing viloations occuring at pin B?

Answer:

Use the following formula:

Tc2q + Tdly3 <= Tsk + Tp - Tsu

Since Tp ( clock frequency is fixed 1/Tp = f ), Tc2q (clock to Q)  and Tsu (setup time) are fixed, the setup timing violations are caused by Tdly3.  In order to fix the setup violations, we can reduce Tdly3.

How will you fix the hold violations occuring at pin B?

Answer:

Use the following formula:

Tc2q + Tdly3 >=  Tsk + Thd
Tc2q + Tdly3 - Tsk >= Thd

Since Tc2q (clock to Q)  and Thd (hold time) are fixed, the hold time violations are caused by the Tdly3. We can increase the Tdly3. For example, add buffer to the path. We should not mess up with the clock skew. It would affect too many paths.


2) If there's a timing violation in the chip, how could you verify it as setup violation or hold time?

Answer:
    
If the test engineer slow the clock speed, the chip passed the tested. It's a setup time problem. If the problem did not changes, it could be hold time issue.

Setup violations occurs when the data path is too slow compared to the clock speed.
The designer can fix the setup violations by reducing the delay in the data path. Designer can also reduce the clock speed to fix the setup violation, but it is going to be a poor design technique.

Hold violations occurs when data is too fast when compared to the clock speed. If hold violations are not fixed before the chip is made, lot of problem occurs unlike setup violation where the clock speed can be reduced. To fix hold violations, designer can add more delay to the data path.

3) what's timing constraint?

   Timing Constraints:

Timing constraints are how the designer tells the STA tool about the timing behavior of the ASIC. The three minimum constraints are defining the clock, input delay, and output delay. There are four types of timing paths are available. They are :

• Input to Register (Sync),
• Register to Register (Sync),
• Register to Output (Sync) and
• Input to Output(Async). Each path has a start and endpoint

When the clocks are defined, all Register to Register paths are assumed to be constrained in one clock cycle. A path originates from either an Input port or a Register clock pin, while an end point is either an Output port or a Register data pin. All start and end point must be timing constrained.