Acronym for Double-Data-Rate Two, which refers to a computer memory technology as it applies to synchronous dynamic random access memory (SDRAM). Standards are defined for the ICs as well as the DIMMs they enable. A single-data-rate SDRAM transfers data on every rising edge of the clock pulse 100MHz. Both DDR and DDR2 are double pumped—they transfer data on the rising and falling edges of the clock, achieving an effective rate of 200MHz with the same clock frequency. The difference between DDR2 to DDR is a doubled bus frequency for the same physical clock rate, which doubles the data rate yet another time.
2) What's DDR3 interface?
DDR3 offers a substantial performance improvement over previous DDR2 memory systems. New DDR3 features, all transparently implemented in the memory controller, improve the signal integrity characteristics of DDR3 designs so that higher performance is achieved without an undue burden for the system designer. If proper consideration is given to any new DDR2 memory design, it can be a relatively easy upgrade to support DDR3 in the next generation design. This paper identified the key differences between DDR2 and DDR3 and illustrated some of the key issues that need to be addressed to easy migration to DDR3.
| DDR | DDR2 | DDR3 | |
| Data Rate | 200-400Mbps | 400-800Mbps | 800-1600Mbps |
| Interface | SSTL_2 | SSTL_18 | SSTL_15 |
| Source Sync | Bidirectional DQS (Single ended default) | Bidirectional DQS (Single/Diff Option) | Bidirectional DQS (Differential default) |
| Burst Length | BL= 2, 4, 8 (2bit prefetch) | BL= 4, 8 (4bit prefetch) | BL= 4, 8 (8bit prefetch) |
| CL/tRCD/tRP | 15ns each | 15ns each | 12ns each |
| Reset | No | No | Yes |
| ODT | No | Yes | Yes |
| Driver Calibration | No | Off-Chip | On-Chip with ZQ pin |
| Leveling | No | No | Yes |
Detail DDR3 interface information
What's ethernet?
Ethernet (the name commonly used for IEEE 802.3 CSMA/CD) is the dominant cabling and low level data delivery technology used in local area networks (LANs). First developed in the 1970s, it was published as an open standard by DEC, Intel, and Xerox (or DIX), and later described as a formal standard by the IEEE. Following are some Ethernet features:
* Ethernet transmits data at up to ten million bits per second (10Mbps). Fast Ethernet supports up to 100Mbps and Gigabit Ethernet supports up to 1000Mbps. Many buildings on the Indiana University campus are wired with Fast Ethernet and the campus backbone is Gigabit Ethernet.
* Ethernet supports networks built with twisted-pair (10BaseT), thin and thick coaxial (10Base2 and 10Base5, respectively), and fiber-optic (10BaseF) cabling. Fast Ethernets can be built with twisted-pair (100BaseT) and fiber-optic (100BaseF) cabling. Currently, 10BaseT Ethernets are the most common.
* Data is transmitted over the network in discrete packets (frames) which are between 64 and 1518 bytes in length (46 to 1500 bytes of data, plus a mandatory 18 bytes of header and CRC information).
* Each device on an Ethernet network operates independently and equally, precluding the need for a central controlling device.
* Ethernet supports a wide array of data types, including TCP/IP, AppleTalk, and IPX.
* To prevent the loss of data, when two or more devices attempt to send packets at the same time, Ethernet detects collisions. All devices immediately stop transmitting and wait a randomly determined period of time before they attempt to transmit again.
What is PCI_Express?
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe (or PCI-E, as it is commonly called), is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP standards. PCIe 2.0 is the latest standard for expansion cards that is available on mainstream personal computers.[1]
PCI Express is used in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals) and as an expansion card interface for add-in boards. A key difference between PCIe and earlier buses is a topology based on point-to-point serial links, rather than a shared parallel bus architecture.
The PCIe electrical interface is also used in a variety of other standards, most notably the ExpressCard laptop expansion card interface.
PCI Express Detail information
What is 10GigE?
The 10 Gigabit Ethernet or 10GE or 10GbE or 10 GigE standard was first published in 2002 as IEEE Std 802.3ae-2002 and is the fastest of the Ethernet standards. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s, ten times as fast as Gigabit Ethernet.
What is QDRII?
It's the same as DDR2
What's RLDRAM II ?
RLDRAM II memory definitely has its advantages for networking applications. For starters, it beats even leading-edge DDR3 for sustainable high bandwidth. It is, after all, a memory device that was originally conceived and designed for networking and L3 cache, high-end commercial graphics, and other applications that require back-to-back READ/WRITE operations or completely random access.
How does RLDRAM memory deliver this kind of performance-critical bandwidth? Significantly lower latency, for one, is a key enabler of random access. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios. And a separate I/O feature reduces turnaround time even further and provides 100% data bus utilization at 1:1 read-to-write ratios. Then there’s bank scheduled auto refresh, which improves bandwidth by enabling the controller to hide refresh commands behind normal operation. And lastly, RLDRAM memory offers more burst length options—2-, 4-, and 8-bit bursts—than DDR3.
Memory Module Definitions
| DDR: | Double Data Rate [Data moves which each edge of the clock] |
| DDR2: | Double Data Rate NOTE [On-Die-Termination, ODT, Architecture Changes] |
| DDR3: | Double Data Rate, third generation |
| DDR-FCRAM: | Double-Data-Rate, Fast-Cycle Random Access Memory [Different core memory arrangement then DDR RAM] |
| DIMM: | Dual In-Line Memory Module. The front side PWB pins are not connected to the rear side pins, pins used for different functions. |
| DRAM: | Dynamic Random Access Memory (Requires Refresh) |
| DRSL: | Differential Rambus Signaling Levels |
| FB-DIMM: | Fully-Buffered DIMM [utilizes JEDEC-standard DDR2 SDRAM] |
| GDDR: | Graphics DDR I/II/III/IV; GDDR1, GDDR2, GDDR3, GDDR4, GDDR5 - 1.25GHz Clock for GDDR4 |
| PSRAM | pseudo-SRAM |
| QBM2 | Quad Band Memory, DDR Compatible at increased speed |
| QDRII: | Quad Data Rate [also called DDR2, DDRII, QDRSRAM, and QDR-2 SRAM] |
| RDIMM | Registered DIMM |
| RIMM | Rambus DIMM [RDRAM], In-stalled in pairs. 16-bit modules are 184-pin or 32-bit modules at 232-pins |
| SDR DRAM: | Single Data Rate SDRAM |
| SIMM: | Single In-Line Memory Module. Data width is 32 bits per memory stick, the front 72 pins and back 72 fingers on the card are connected together. While DIMM pins are not. |
| SODIMM: | Small Outline Dual In-Line Memory Module [used in Laptops / Notebooks] |
| SOCDIMM: | Small-Outline Clocked DIMM, ultra-narrow SODIMM form factor |
| SORDIMM: | Small-Outline Registered DIMM, ultra-narrow SODIMM |
| SRAM: | Static Memory; Faster than DRAM, but more expensive |
| UDIMM | UnBuffered DIMM |
| ULP-DIMM | Ultra Low Profile DIMM [small form factor DDR/DDR2 Server/Routers/Switch memory] |
| VLP-DIMM | Very Low Profile DIMM [small form factor DDR/DDR2 Server/Routers/Switch memory] |
| XDR: | Memory sticks using DRSL [also called XDIMM], Memory type from RAMbus |
| XDR2: | Memory type from RAMbus |
| ZB-DDR: | Zero-Buffer DDR |
| HDIMM | .... |
| CAS Latency: | Column Access Strobe, is the relationship between Column Access Time and Clock Cycle Time. |
| CAS-2: | wait 2 clock cycles after the Column Address before the data appears. CAS-3, wait 3 clock cycles. |
| ECC: | Error Correcting Code, an additional 8 bits [to 64-bit data] of ECC for a total of 72-bits [72-bit wide data] |
| Bank | The DRAMs on a module are organized into a number of Banks that can be accessed simultaneously. |
| Rank | Defines a set of DRAM chips (on a module) comprising 8 byte wide (64 bits) data, or 9 bytes (72 bits) with ECC. All devices in a Rank are connected by a single Chip-Select. The actual memory size is not defined. Single-sided memory modules are always Single-Rank. Double-sided unbuffered DIMMs and SODIMMs are always Dual-Rank. Server DIMMs may have up to 4 ranks. |
| Dual Rank | Defines 2 sets of DRAM chips (on a module) each comprised of 8 byte wide (64 bits) data, or 9 bytes (72 bits) with ECC. All devices in a Rank are connected by a single Chip-Select. The actual memory size is not defined. Normally a module will have one rank per PWB side. |
| Quad Rank | Defines 4 sets of DRAM chips (on a module) each comprised of 8 byte wide (64 bits) data, or 9 bytes (72 bits) with ECC. All devices in a Rank are connected by a single Chip-Select. The actual memory size is not defined. Normally a module will have two ranks per PWB side. |
| Registered DIMM | Buffers the Address and Clock signals on each DIMM to enhance the signal quality. RDIMM |
| SO: | Small Outline (Memory Module), as in SO-DIMM |
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