ASIC Gate Interview Questions Part #2

1) Deriving the vectors for the stuck at 0 and stuck at 1 faults.

•  A line l is stuck at a fixed logic value v (v {0,1}), denoted by l/v;

(we say also: a line has a fault stuck-at-1 (s-a-1) or stuck-at-0 (s-a-0);

examples:

• a short between ground (s-a-0) or power (s-a-1) and a signal line;
• an open on a unidirectional signal line;
• any internal fault in the component driving its output that it keeps a constant value;
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The detectable error can be tested by applying different vectors to the circuit. The combination logic will pass the errors if there's any stack-at-1 or stack-at-0 errors.


Some errors could not be detectable because the error could not passed to the result logic. It need additional tests to catch this errors.


The testing based on stuck at fault model is aided by several things:
1) A test developed for a single stuck at fault often finds a large number of other stuck at faults.
2) A series of tests for stuck at faults will often, purely by serendipity, find a large number of other faults, like the stuck-open faults. This is sometimes called "windfall" fault coverage.
3) Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit changes, when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem.




2) minimize a boolean expression:


    Use Karnaugh Maps to minimize the logic. 


    For example:




   

3) What's the latchup effect?

Latchup is a term used in the realm of integrated circuits (ICs) to describe a particular type of short circuit which can occur in an improperly designed circuit. More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.








Preventing latchup
Fab/Design Approaches

1. Reduce the gain product b1 x b1
• move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces gain beta2 ­> also reduces circuit density
• buried n+ layer in well reduces gain of Q1
2. Reduce the well and substrate resistances, producing lower voltage drops
• higher substrate doping level reduces Rsub
• reduce Rwell by making low resistance contact to GND
• guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic resistances. 

Systems Approaches

1. Make sure power supplies are off before plugging a board. A "hot plug in" of an unpowered circuit board or module may cause signal pins to see surge voltages greater than 0.7 V higher than Vdd, which rises more slowly to is peak value. When the chip comes up to full power, sections of it could be latched.
2. Carefully protect electrostatic protection devices associated with I/O pads with guard rings. Electrostatic discharge can trigger latchup. ESD enters the circuit through an I/O pad, where it is clamped to one of the rails by the ESD protection circuit. Devices in the protection circuit can inject minority carriers in the substrate or well, potentially triggering latchup.
3. Radiation, including x-rays, cosmic, or alpha rays, can generate electron-hole pairs as they penetrate the chip. These carriers can contribute to well or substrate currents.
4. Sudden transients on the power or ground bus, which may occur if large numbers of transistors switch simultaneously, can drive the circuit into latchup. Whether this is possible should be checked through simulation.